Datapath and Microoperations

A digital computer is defined internally by its registers, the microoperations performed on their stored values, and the control functions that initiate those microoperations. Register-transfer language makes that behavior precise without descending immediately to individual gates.

Timing rule: the right-hand side of a register-transfer statement is evaluated from the old state during a clock interval; the destination changes at the active edge.

Register-Transfer Language

The statement

means that the binary content of source register $R_1$ is copied into destination register $R_2$. $R_1$ is unchanged; the previous content of $R_2$ is overwritten. The notation assumes a path from $R_1$ to $R_2$ and a parallel-load input on $R_2$.

Register names may be annotated:

• $MAR$ denotes a register by its function;
• $R_2(0\text{-}7)$ denotes a selected part;
• $R_2(L)$ and $R_2(H)$ may denote low and high portions;
• a comma separates microoperations that occur concurrently, as in $R_2\leftarrow R_1,\ R_4\leftarrow R_3$.

Two transfers separated by a comma are legal in one interval only if the datapath has the required independent sources, destinations, and write ports.

Conditional transfer

means “if control function $P=1$, load $R_2$ from $R_1$ at the next active edge.” It is equivalent to the Boolean control statement

The source output can change combinationally before the edge without changing $R_2$. Setup and hold constraints require the selected value and load enable to remain stable around that edge.

Common Bus Systems

Dedicated wires between every pair of registers scale poorly. A common bus lets many registers share one set of word-wide lines.

For registers $A,B,C,D$, source select $S_1S_0$ may use:

To perform $R_2\leftarrow C$, the controller selects $C$ onto the bus and asserts LoadR2:

The two symbolic actions describe one physical transfer: source selection is combinational; destination loading is clocked.

Bus hardware grows with both register count and word width. Eight 16-bit source registers require sixteen 8-to-1 multiplexers—one for each bus bit—and $\log_2 8=3$ shared source-select bits. Destination selection is separate: a 3-to-8 decoder can produce eight one-hot load enables. This separation is why several destinations may capture one selected source, while two different sources cannot occupy a single bus simultaneously.

Three-state bus

A multiplexer bus may be replaced by one three-state buffer per source bit. A buffer output can be 0, 1, or high impedance $Z$. Exactly one register’s buffers may be enabled at a time:

• no enabled source leaves the bus floating unless pull or hold circuitry is provided;
• two enabled sources can contend, producing an invalid level and excessive current;
• decoder-generated one-hot enables prevent contention.

Memory Transfers

$M[AR]$ denotes the memory word whose address is held in address register $AR$.

A read does not destroy the memory word. A write changes memory state and therefore must not be asserted until address and data are stable.

Four Classes of Microoperations

1. Register transfer: copy binary information.
2. Arithmetic: interpret words as numbers and add, subtract, increment, or decrement.
3. Logic: manipulate corresponding bits without numeric carry.
4. Shift: move bit positions logically, arithmetically, or circularly.

The classes describe meaning. One physical ALU may implement several classes by changing its select inputs.

Arithmetic Microoperations

Parallel adder

An $n$-bit ripple-carry adder chains $n$ full adders:

$C_{i+1}$ must propagate to the next stage. This makes ripple delay grow with word width.

Adder-subtractor

A common circuit uses mode $M$ to complement every $B$ input and supply the initial carry:

For unsigned subtraction, final carry 1 means no borrow. For two’s-complement signed arithmetic, carry out is not the overflow test:

For example, with four bits, $7+3$ gives 0111 + 0011 = 1010. The carry into the sign bit is 1 and the carry out is 0, so $V=1$: two positive operands produced a negative four-bit pattern.

Increment and decrement

Increment is $R\leftarrow R+1$. A chain of half adders can propagate the initial 1, or an existing adder can use a zero second operand and $C_{in}=1$. Decrement may add an all-ones word:

Multifunction arithmetic circuit

If multiplexers choose $Y\in\{0,B,\overline B,11\ldots1\}$, one parallel adder computes $D=A+Y+C_{in}$:

Logic Microoperations

Logic operations act independently on bit pairs. If $A=1100$ and $B=1010$:

AND can clear selected bits, OR can set selected bits, XOR can toggle selected bits, and a mask can isolate a field. All 16 Boolean functions of two variables are possible, but an ALU commonly implements a useful subset.

Shift Microoperations

For 10110110:

• logical right → 01011011;
• arithmetic right → 11011011;
• rotate right → 01011011 because the old low bit happened to be 0.

Arithmetic Logic Shift Unit

A typical control word contains:

Suppose $A=0101$, $B=0011$, the arithmetic function is add, carry in is 0, and shift is logical right. The combinational stages produce:

The destination remains unchanged during the interval and becomes 0100 only on the active edge.

Timing one microoperation

For $R_3\leftarrow R_1+R_2$, the active path may be source register $\rightarrow$ operand multiplexers $\rightarrow$ ALU $\rightarrow$ destination register. Suppose the delays are:

Ignoring skew, the clock period must be at least

$T_{clock}=80+140+350+70=640\text{ ps},$

so this datapath cannot exceed about $1/640\text{ ps}=1.56$ GHz. A logic AND using a 90 ps ALU path finishes sooner, but a common clock must still accommodate the slower addition. Pipelining can divide the long path, at the cost of extra registers, latency, and control complexity.

Datapath Resource Conflicts

With one common bus, only one source can drive it during an interval. The simultaneous transfers

cannot both occur if they require different bus sources. The controller must use two cycles or the datapath must provide a second read path. Register-transfer notation is therefore also a resource specification.

Self-Check

1. Which part of $P:R_2\leftarrow R_1$ is combinational and which part is clocked?
2. Why are $C_n$ and signed overflow different?
3. For $A=1001$ and $B=0011$, compute $A-B$ with four-bit two’s-complement addition.
4. Can two destination registers load the same bus value on one edge?
5. How many bit-slice multiplexers and select bits are required to place one of 16 different 32-bit registers on a common bus?