Control Unit Design

A processor datapath can add, complement, shift, load, and clear values, but it does not decide when those operations happen. The control unit supplies that sequence. It observes an operation request and datapath status, enters a state, asserts the corresponding control signals, and moves to the next state on a clock edge.

This chapter develops that idea through two complete hardwired-control examples. The first uses one flip-flop per state to control sign-magnitude addition and subtraction. The second encodes four multiplication states in two flip-flops. The examples expose the same reusable design path:

algorithm -> datapath -> state diagram -> control table -> Boolean logic

Central idea: the datapath performs microoperations; the controller sequences them. A correct arithmetic algorithm is not yet a hardware design until every operation has a destination register, a control signal, a state, and a clock edge.

Control-Unit Foundations

Datapath and controller

The two parts form a synchronous feedback loop. The controller says what to do now; the datapath reports what just happened.

The visual key is consistent throughout the chapter: blue identifies stored state and registers, teal identifies control and decisions, amber identifies arithmetic or datapath actions, and purple identifies status, correction, and shift operations. The colours explain hardware roles; the connections and branches retain the structure of the source figures.

A microoperation is an elementary register action completed in one clock interval, such as $A \leftarrow A+B$, $E \leftarrow 0$, or $AQ \leftarrow \operatorname{shr}(EAQ)$. Register-transfer notation names the destination on the left and the value computed during that interval on the right.

Suppose $A=0101_2$ and $B=0011_2$. While the controller is in an “add” state, it selects the ALU’s add function and asserts the load enable for $A$. The ALU output changes combinationally to 1000, but the stored value of $A$ remains 0101 until the active clock edge. At that edge, $A$ becomes 1000 and the controller enters its next state.

during the interval: current state -> control signals -> ALU result
at the clock edge:   registers load result; state register loads next state
after the edge:      new state and new register values are visible

This “compute during the interval, commit at the edge” model explains why a status value written by one state is normally tested by the following state.

From an algorithm to hardware

1. Write the algorithm. Show operations, decisions, repetition, and termination.
2. Specify the datapath. Choose registers and functional units, then name every control input and status output.
3. Assign control states. A state groups compatible microoperations that can occur on one active clock edge.
4. Draw transitions. Label every conditional edge and account for every input combination.
5. Create the output table. For each state, identify the required datapath control word.
6. Choose an encoding. Use one-hot, binary, Gray, or another justified assignment.
7. Derive and verify logic. Obtain next-state and output equations, then trace normal and boundary cases.

The conversion from flowchart to state diagram is not unique. Two controllers may implement the same algorithm with different state counts. A valid choice must still respect hardware constraints: a register cannot be loaded before its source is ready, a status bit written on an edge cannot be tested before the following state, and incompatible transfers cannot share one resource in the same cycle.

Example 1: Sign-Magnitude Addition and Subtraction

Problem and notation

Two sign-magnitude operands are split into sign bits $A_s,B_s$ and magnitude registers $A,B$. The controller accepts separate add and subtract requests.

With a four-bit magnitude, the representation has one separate sign bit:

The magnitude is ordinary unsigned binary. The sign bit is not part of a two’s-complement word. This is why the hardware must decide separately what to do with the signs and the magnitudes—and why sign-magnitude has two encodings for zero.

Subtraction is reduced to addition by first complementing $B_s$. The controller can then apply one common rule: add magnitudes when the effective signs match; otherwise subtract the smaller magnitude from the larger one.

The design assumes $q_a$ and $q_s$ are mutually exclusive request pulses. If an interface can assert both—or hold either request high after completion—the controller needs explicit priority and acknowledgement rules.

Reading the algorithm

• With equal effective signs, compute $A\leftarrow A+B$. The sign $A_s$ already belongs to the result, and $E\leftarrow C_{out}$ records magnitude overflow.
• With unlike signs, compute $A\leftarrow A+\overline B+1$. This is $A-B$ using two’s-complement addition. Ordinary signed overflow is not possible in this branch.
• If the subtraction produces an end carry, there was no borrow: the magnitude in $A$ is already non-negative. Clear $E$ and retain $A_s$.
• If there is no end carry, then $|A|<|B|$. The register contains a negative two’s-complement intermediate value. Complement and increment $A$ to recover its magnitude, then complement $A_s$ so the sign follows the operand with the larger magnitude.

The correction is split into $A\leftarrow\overline A$ and $A\leftarrow A+1$ because the available ALU provides complement and increment, but not a single “two’s complement” function. When the magnitudes are equal, the subtraction magnitude is zero; a practical design should also define whether zero is canonicalised to a positive sign.

Numeric examples: every arithmetic path

Use four-bit magnitude registers throughout these examples:

The datapath does not contain a magnitude comparator. It discovers which magnitude is larger from the carry produced by two’s-complement subtraction.

For $+5+(-3)$, $A_s=0$, $B_s=1$, so $S=1$ and the controller subtracts:

  A              0101
  complement B   1100
  input carry    0001
                 ----
                 1 0010

The stored magnitude is 0010 and $E=1$. End carry 1 means no borrow, so $|A|\ge|B|$; the sign stays $A_s=0$, producing $+2$.

For $+3+(-5)$, the same circuit produces a negative intermediate result:

  A              0011
  complement B   1010
  input carry    0001
                 ----
                   1110   E = 0

  complement     0001
  increment      0010
  flip A_s       0 -> 1

No end carry means a borrow occurred and $|A|<|B|$. States $T_6$ and $T_7$ convert 1110 to magnitude 0010 and reverse the sign, producing $-2$.

A subtraction request only changes the effective sign of $B$. For example, $+5-(-3)$ first changes $B_s$ from 1 to 0; the controller then sees equal signs and adds the magnitudes, obtaining $+8$.

Finally, four magnitude bits can hold at most $15$. For $+9+(+8)$, 1001 + 1000 = 1 0001: $A$ receives 0001, while $E=1$ reports that the mathematical result $17$ did not fit. The carry must be interpreted as overflow in the equal-sign addition path, not as a fifth magnitude bit silently discarded.

Datapath specification

The ALU receives $A$, $B$, the selection word $s_2s_1s_0$, and input carry $C_{in}$. Signal $L$ loads the ALU result into $A$ and $C_{out}$ into $E$. Three direct controls handle operations outside the ALU:

The controller inputs are $q_a$, $q_s$, $S$, and $E$. Although $A_s$ and $B_s$ enter the comparison logic physically, using $S=A_s\oplus B_s$ reduces the controller’s sign decision to one variable.

Control-state diagram

The state sequence is deliberately explicit:

• $T_0$ is idle and asserts $x$. It stays there while both requests are low.
• A subtract request enters $T_1$ to complement $B_s$; an add request can go directly to $T_2$.
• $T_2$ tests the updated sign relation $S$. Matching signs select $T_3$; unlike signs select $T_4$.
• $T_3$ adds magnitudes and finishes. $T_4$ subtracts magnitudes and stores the end carry.
• $T_5$ clears overflow status and chooses whether result correction is needed.
• $T_6$ and $T_7$ form the two’s complement of $A$ and reverse $A_s$ before returning to idle.

The value $E\leftarrow C_{out}$ is written on the edge that leaves $T_4$. Therefore the controller tests $E$ in $T_5$, not in $T_4$. Clearing $E$ while leaving $T_5$ is safe: the old value selects the outgoing edge during the interval, and the edge simultaneously stores the next state and clears $E$.

Clock trace: positive 3 plus negative 5

The numeric example becomes a hardware execution when placed on clock intervals. Initial values are $A_s=0$, $A=0011$, $B_s=1$, $B=0101$ and $q_a=1$:

There are six state intervals from accepting the request to becoming ready again. Only three intervals change arithmetic data: $T_4$, $T_6$, and $T_7$. The other intervals route the controller using conditions that are stable for the entire interval.

State outputs and microoperations

The load signal $L$ must be 1 whenever an ALU result is intended to change $A$ (and, where relevant, $E$). In other states, the ALU may still produce a combinational value, but it has no architectural effect.

One-hot implementation

Assign one D flip-flop to each state and use the flip-flop output itself as the timing variable $T_i$. Exactly one state bit is high. To obtain a D-input equation, AND each incoming transition condition with its source state and OR all paths entering the destination:

Read each equation as an answer to “when must this state become 1?” For example:

• $T_2$ is entered from $T_0$ when $q_a=1$, or from $T_1$ unconditionally. Therefore $D_{T_2}=q_aT_0+T_1$.
• $T_6$ is entered only from $T_5$ when $E=0$. Therefore $D_{T_6}=\overline ET_5$.
• $T_0$ has four incoming paths: its idle self-loop, completion from $T_3$, the $E=1$ branch from $T_5$, and completion from $T_7$. OR-ing those products gives $D_{T_0}$.

Output equations are even more direct: OR the states whose table row contains 1 for that signal.

As a quick check, let the current state be $T_4$. Then only $T_4=1$, so $s_2s_1s_0=010$, $C_{in}=1$, and $L=1$. Those are exactly the controls required for $A\leftarrow A+\overline B+1$. In $T_2$, none of the ALU or load equations is asserted; that state exists only to choose the next path.

One-hot control uses eight flip-flops here, but the logic is regular and can be read directly from the state diagram. A compact binary assignment would use only three flip-flops, at the cost of decoding states and usually more intricate next-state logic.

Example 2: Shift-and-Add Binary Multiplication

Datapath algorithm

Let $B$ hold the multiplicand, $Q$ hold the multiplier, $A$ accumulate the partial product, $E$ hold the adder carry, and $P$ count the remaining bit positions. The final $2k$-bit magnitude appears in the concatenated registers $AQ$. The result sign is $A_s\leftarrow B_s\oplus Q_s$.

For $k=4$, the shift register is nine bits wide: one carry bit, four accumulator bits, and four multiplier bits. If EAQ = 0 0101 0011, one right shift produces 0 0010 1001. The old least-significant bit of $A$ becomes the new most-significant bit of $Q$; the old $E$ becomes the new most-significant bit of $A$. This is why $E$ must participate in the shift rather than being discarded after an addition.

On a multiply request $q_m$:

1. Initialise $A\leftarrow0$, $E\leftarrow0$, $P\leftarrow k$, and set the product sign.
2. Inspect $Q_1$, the current least-significant multiplier bit. If it is 1, perform $A\leftarrow A+B$ and $E\leftarrow C_{out}$.
3. Always perform $P\leftarrow P-1$.
4. Shift the concatenated value: $AQ\leftarrow\operatorname{shr}(EAQ)$, then clear $E$.
5. If $P\ne0$, repeat from the bit test; otherwise return to idle.

Each shift places one newly settled product bit into $Q$ and exposes the next multiplier bit at $Q_1$. After $k$ iterations, $A$ contains the most-significant half and $Q$ the least-significant half. $P_z$ denotes the zero test: $P_z=1$ exactly when $P=0$.

The useful invariant is: before iteration $i$, the unprocessed multiplier bits remain in $Q$, while the partial product accumulated so far occupies the left side of $AQ$. Testing $Q_1$ decides whether the current power-of-two copy of $B$ contributes to the product; the shift then aligns the registers for the next bit.

Four-state controller

The conditional control function for loading the sum is $L=Q_1T_2$. In contrast, the decrement is enabled by $T_2$ alone. Moving the decrement into $T_2$ makes the new counter value available for the $P_z$ decision in $T_3$.

Worked trace: multiplying 5 by 3

For $k=4$, begin with $B=0101$, $Q=0011$, $A=0000$, and $E=0$:

Look closely at iteration 1. Because $Q_1=1$, the datapath first adds 0000 + 0101, making E:A = 0:0101. It then shifts the complete string 0 0101 0011 to 0 0010 1001. Reversing those two actions would produce a different—and incorrect—partial product.

The final concatenation is $AQ=0000\,1111_2=15_{10}$. If the original operands were $-5$ and $+3$, the magnitude trace would be identical; only $A_s=B_s\oplus Q_s=1$ would change, so the interpreted result would be $-15$.

The carry register matters when an addition exceeds four bits. If $A=1100$ and $B=1010$, their sum is 1 0110. Storing E:A = 1:0110 and then shifting preserves the leading 1 as the new most-significant bit of $A$.

Encoded-state excitation table

Encode $T_0,T_1,T_2,T_3$ as $00,01,10,11$ in state bits $G_2G_1$. For JK flip-flops, X is a don’t-care excitation:

Apply these four rules independently to $G_2$ and $G_1$ in every state-table row.

Inspection and simplification give:

Here is how to read the result:

• $G_2$ must change from 0 to 1 only when leaving $T_1$, so $J_{G_2}=T_1$.
• $G_2$ must reset while leaving $T_3$ only when the counter is zero, so $K_{G_2}=T_3P_z$.
• $G_1$ must set for the request transition $T_0\rightarrow T_1$ and for $T_2\rightarrow T_3$, so $J_{G_1}=T_0q_m+T_2$.
• Whenever $G_1=1$—in $T_1$ or $T_3$—the next state’s $G_1$ is 0. Choosing $K_{G_1}=1$ therefore handles both cases; its value is irrelevant while $G_1=0$.

Equations derived by inspection are candidates, not proof. Substitute every table row—or simulate all reachable state/input combinations—to confirm that the resulting circuit produces the specified transitions. This four-state example uses every two-bit encoding; a controller with unused encodings should also define a safe recovery path, usually to the idle state.

PLA and ROM Control

A hardwired controller combines a state register with fixed gates and decoders. The combinational part can instead be replaced by a programmable logic array (PLA). The state register still holds the current control state; the PLA receives that state plus external/status inputs and produces both the next-state bits and datapath control outputs.

The state table already contains the information needed to create a PLA program table or a ROM truth table:

address/input side: current state + requests + status
data/output side:   next state + datapath controls

A PLA is attractive when shared product terms and don’t-care entries reduce the logic. A ROM is often simpler when most combinations need explicit outputs. In both cases, “programmable” refers to the combinational mapping; the clocked state register still determines the control sequence.

For a concrete sizing comparison, the multiplier has two state bits and two relevant inputs, $q_m$ and $P_z$. A ROM indexed by all four bits needs $2^4=16$ words. If the controller needs two next-state bits and six datapath controls, each word is eight bits, for a total of $16\times8=128$ stored bits—even though several address combinations behave identically. A PLA can express only the required product terms, such as $T_1$, $T_3P_z$, and $T_0q_m$, and share them between outputs. The ROM is more regular; the PLA may be smaller when the table is sparse.

A Controlled Accumulator Bit Slice

A compact accumulator unit shows how a control word becomes gates. Nine mutually exclusive variables select one register operation:

For each bit $i$, combinational logic forms the requested next value $A_i^+$. A D flip-flop could load that value directly. With a JK flip-flop, the excitation can be written $J_i=\bar A_iA_i^+$ and $K_i=A_i\bar A_i^+$. Because the controls are mutually exclusive, their candidate next values can be ORed without two operations fighting for the same destination.

The add and increment terms propagate carry from bit $i$ to $i+1$; shift-right takes $A_{i+1}$, shift-left takes $A_{i-1}$, with defined serial inputs at the ends. A zero-status output is

$Z=\overline{A_0\lor A_1\lor\cdots\lor A_{n-1}}.$

This slice is the gate-level version of a control table: each symbolic transfer must have a data path, and each $p_j$ must activate exactly that path at the clock edge.

From Arithmetic Control to CPU Control

An instruction controller uses exactly the same construction at a larger scale. Its datapath adds a program counter, instruction register, memory interface, register file, and condition flags. A simple multicycle fetch might be divided as follows:

An opcode plays the role of an operation request; zero, carry, overflow, and comparison flags play the role of $S$, $E$, $Q_1$, and $P_z$; and the controller outputs become mux selects, ALU functions, memory enables, and register write enables. Pipelining later overlaps these phases, but it does not remove the need to generate correct control for each stage.

For example, suppose PC = 0x20 and memory location 0x20 contains ADD R3, R1, R2, with R1 = 9 and R2 = 6:

The arithmetic is simple; the controller’s job is to guarantee that the correct sources, destination, ALU function, and write enable are selected in the correct intervals. A mistaken R3 write enable one interval early would store an old value even if the ALU itself were perfect.

Design Checks and Refinements

Before treating a controller as complete, check the following:

• Idle protocol: Is there a ready signal, and what happens if requests overlap or remain asserted?
• Complete transitions: Does every reachable state define a next state for every relevant condition?
• Clock semantics: Is each decision based on a value that was already stored before the active edge?
• Control safety: Are incompatible enables mutually exclusive, and are write enables low when results should be ignored?
• Arithmetic boundaries: What happens for zero, equal magnitudes, maximum carry, negative zero, and the most negative representable value?
• Counter convention: Is the loop count tested before or after decrement, and does the controller run exactly $k$ iterations?
• Reset and recovery: Which state is entered after reset, and can an illegal encoded state return safely to idle?
• Equation verification: Do the simplified equations reproduce every state-table row, including intended don’t-cares?

The two examples differ in arithmetic and encoding, but their architecture is the same: status flows from datapath to controller, control flows back to datapath, and the state register turns an algorithm into a clock-by-clock sequence. That pattern scales from a small arithmetic unit to the instruction fetch-decode-execute controller of a CPU.

Quick self-check

1. Why is $E$ tested in $T_5$ rather than in $T_4$?
2. For $-6+(+2)$, which arithmetic branch runs, and what sign should the result have?
3. In the multiplier, why is the shift applied to EAQ rather than only AQ?
4. Which term in $D_{T_0}$ keeps the sign-magnitude controller idle when no request is present?