Computer Organization

Computer architecture explains the contract visible to a programmer and the structures that make that contract run. The subject therefore connects two views:

```text program and data → instruction-set contract → processor organization → digital hardware ```

Central idea: architecture specifies what a machine does; organization explains how a particular machine does it.

Architecture, Organization, and Implementation

The terms are related but not interchangeable.

Two processors may implement the same architecture while using different organizations. A program sees the same instructions, but one processor might use a five-stage pipeline and another a deeper pipeline with larger caches. Conversely, changing an instruction encoding changes the architecture because machine-code programs can observe it.

Firmware sits between ordinary software and hardware. It is program logic retained when power is removed and is normally changed less often than application software. Modern firmware can be updated, but its persistence and close relationship with a device distinguish it from ordinary programs.

Functional Units

Input and output

Input units translate information from the external world into the binary representation used internally. Output units perform the reverse translation. Peripherals differ greatly in speed and representation, so an interface unit supplies data registers, status information, and timing control between a peripheral and the processor.

Memory

Memory stores both instructions and data. Each location has an address, and a read or write operation selects one location at a time. If a memory contains $2^n$ addressable locations, it needs $n$ address bits. A `64 KiB` byte-addressable memory therefore has $2^{16}$ locations and a 16-bit address.

Processor

The processor contains:

• a control unit, which fetches and decodes instructions and generates enabling signals;
• an arithmetic logic unit (ALU), which performs arithmetic, logical, and comparison operations;
• registers, which hold operands, addresses, instructions, status, and intermediate results close to the ALU.

The control unit is not normally the source of operand data. It selects routes and operations. The datapath—registers, buses, ALU, and shifter—carries and transforms the values.

Three Kinds of Information Flow

Treating every line as “data” hides the design problem. For a load instruction, an address must first become valid, a read command must be asserted, memory must return data, and only then may the destination register load.

The Stored-Program Operational Concept

Instructions and ordinary data reside in memory as binary words. The program counter ($PC$) identifies the next instruction. The instruction register ($IR$) holds the current instruction while it is decoded and executed.

Fetch

A representative fetch uses temporary memory registers:

The transfers cannot all be assumed instantaneous. $MAR$ must hold a stable address while memory is read; $MDR$ captures the returned word; $IR$ then preserves the instruction for decoding.

Decode and operand access

The opcode field selects the operation. Addressing-mode and operand fields identify registers, constants, or memory locations. An effective address may require an additional ALU calculation before the operand can be fetched.

Execute and write-back

For an arithmetic instruction, the control unit selects operands, chooses an ALU function, and enables the destination register. For an I/O instruction, it enables the appropriate interface. A branch may replace $PC$ rather than writing an arithmetic result.

Interrupt check

After an instruction reaches a safe completion point, the processor may test pending enabled interrupts. If one is accepted, it saves enough state to resume later and transfers control to an interrupt-service routine.

A Complete Numeric Trace

Suppose memory contains:

Initially $PC=\texttt{0x020}$. The visible effects are:

The architecture describes these effects. The organization determines whether the operand comes through a shared bus, how many clock cycles each instruction needs, and whether the memory reference hits in a cache.

Measuring Execution Time

A useful first processor-performance equation is

If a program executes $2.0\times10^9$ instructions at an average CPI of $1.5$ on a $3.0\text{ GHz}$ processor,

A higher clock rate alone does not guarantee a faster program: instruction count and CPI may change with the architecture, compiler, caches, and pipeline. Throughput—the amount of work completed per unit time—is also different from the latency of one task.

Comparing processors correctly

For one fixed workload, performance is the reciprocal of execution time. If machine A completes it in $T_A$ and machine B in $T_B$, then

Suppose the same compiled program executes $1.2\times10^9$ instructions on two processors:

Although B has the higher clock rate, A is $0.75/0.60=1.25$ times as fast for this program. A fair comparison must hold the workload constant and account for instruction count, CPI, and clock period together. Wall-clock time may additionally include operating-system delay and I/O; the CPU-time equation models time spent executing on the processor.

Abstraction Without Mystery

Each level depends on the one below it:

1. Applications express algorithms.
2. Compilers translate them into an instruction set.
3. The processor organizes register transfers to implement each instruction.
4. Digital circuits implement the registers, ALU, memory, and control.

An abstraction hides detail, but it does not remove causality. A cache miss, branch hazard, or slow I/O transfer becomes visible when lower-level timing changes program performance.

Design Checklist

When reading any architecture diagram, ask:

1. Which elements store state?
2. Which elements compute combinational results?
3. Where do addresses travel?
4. Where do operands and instructions travel?
5. Which control signal makes each transfer permanent?
6. On which clock edge does the new state become visible?

If those six questions have concrete answers, the diagram describes an executable machine rather than a collection of boxes.

Self-Check

1. Classify “the instruction has a 12-bit address” and “the memory uses DRAM chips” as architecture or organization.
2. How many address bits are required for a byte-addressable `4 MiB` memory?
3. Why must the instruction register retain the fetched instruction after memory begins servicing another address?
4. A program has $8\times10^8$ instructions, CPI $=2.25$, and clock rate $=1.8$ GHz. Find its CPU time.
5. If one processor finishes a workload in 12 s and another in 8 s, what is the second processor’s speedup?