Input Output Systems

Peripherals differ from the CPU in speed, data format, electrical signaling, and timing. An I/O interface absorbs those differences so the processor sees regular data, status, and control registers rather than device-specific signals.

Interface Module

The device side may include a transducer: a keyboard converts motion to a code; a display converts bits to light. The system side uses the address, data, and control buses.

With memory-mapped I/O, interface registers occupy normal address space and ordinary loads/stores access them. With isolated I/O, a separate address space and special I/O instructions distinguish device transfers.

Asynchronous Data Transfer

The CPU bus and a peripheral usually do not share one clock. A transfer needs a timing convention.

Strobe control

• Source-initiated: source places data, asserts strobe, then removes strobe and data after the specified interval.
• Destination-initiated: destination asserts strobe/request; source responds by placing data.

The single control line assumes a bounded response time. If a device is missing or too slow, no acknowledgement reports the failure.

Handshaking

For source-initiated transfer:

1. Source places data and asserts REQ/data-valid.
2. Destination captures data and asserts ACK.
3. Source removes REQ and data.
4. Destination removes ACK; the channel is ready again.

This four-phase protocol tolerates arbitrary relative speeds. A destination-initiated version begins with a ready/request from the receiver. Synchronizers are still needed where an asynchronous control enters clocked logic.

Modes of I/O Transfer

Memory is ultimately the source or destination of bulk information; the processor transforms it. The question is how much CPU involvement moves each word.

Programmed input resembles:

while READY == 0:        // busy wait
    continue
R1 ← DATA_IN
READY ← 0

It is simple, but the CPU repeatedly reads status. Interrupt-driven I/O lets useful computation continue and requests service only when needed.

For scale, moving a 1 MiB block as 4-byte words requires $1{,}048{,}576/4=262{,}144$ transfers. If a polling loop and move consume eight instructions per word, the CPU executes about $2.10$ million instructions just to copy the block. DMA replaces that per-word work with setup and completion handling; the bus still transfers every byte, but the CPU is free between those two events.

Interrupt Sequence and Priority

At an accepted interrupt, the processor completes a defined boundary, saves a return address and necessary state, identifies the source, disables or masks unsafe nesting, and loads the handler address. The interrupt service routine (ISR) services the device and restores the interrupted context.

Priority determines which simultaneous request is serviced first and which sources may preempt a current handler. High-rate devices such as storage normally outrank slow human-input devices.

A parallel unit commonly uses an interrupt-request register $IR$, mask register $IM$, and priority encoder:

$P_i=IR_i\land IM_i.$

The encoder selects the highest active $P_i$ and supplies a vector or identification code.

ISR housekeeping

Entry may mask lower-priority sources, clear interrupt status as required, save processor registers, then re-enable higher-priority interrupts. The source-specific service follows. A safe exit sequence is:

1. Clear global interrupt enable IEN.
2. Restore processor registers.
3. Clear the serviced source’s request bit.
4. Restore lower-priority mask bits.
5. Restore the return PC and set IEN.

Interrupts must not be accepted during the critical restore interval; otherwise the return address or saved state can become ambiguous. Hardware stacking can reduce this latency, but it does not remove the logical requirements.

Direct Memory Access

DMA removes the CPU from the per-word data path. A DMA controller becomes bus master and transfers directly between a peripheral and memory.

Controller registers and signals

The CPU initializes four items: starting memory address, word count, read/write mode, and start control. After that, it need not communicate again until completion, error, or an optional progress check.

DMA Transfer Sequence

1. Peripheral asserts DREQ.
2. DMA asserts bus request BR.
3. CPU completes its current instruction, places address/data/read/write outputs in high impedance, and asserts BG.
4. DMA drives its address register onto the address bus, asserts memory RD or WR, and acknowledges the peripheral with DACK.
5. The device supplies or receives the data word.
6. DMA increments address, decrements word count, and tests zero.
7. If words remain, repeat according to the selected mode. At zero, remove BR and interrupt the CPU.

Suppose a 1024-word input block begins at 0x8000. CPU initializes ADDR=0x8000, COUNT=1024, direction device-to-memory. After 300 successful words, ADDR=0x812C and COUNT=724 (assuming word-address increments of one). At completion, ADDR=0x8400, COUNT=0, and memory locations 0x8000–0x83FF hold the block.

Burst and cycle stealing

• Burst: DMA holds the bus for the complete block. Throughput is high, but the CPU cannot use the bus during the burst.
• Cycle stealing: DMA transfers one word, releases the bus, and requests again later. CPU progress is slowed by individual stolen memory cycles rather than stopped for a whole block.
• Transparent/background DMA: transfer only when the CPU is not using the bus, reducing interference at the cost of variable device throughput.

A multi-channel DMA controller gives each channel request/acknowledge signals and usually separate address/count state. Internal priority selects a channel when requests coincide.

I/O Processor

An I/O processor (IOP) is a processor specialized for I/O with direct-memory access. Unlike a DMA controller, which the CPU configures completely for a fixed transfer, an IOP fetches and executes its own I/O instructions. It can branch, perform arithmetic/logic, translate codes, manage protocols, and coordinate several devices.

The CPU initiates an I/O program and the IOP proceeds independently, sharing central memory with the CPU. This divides responsibilities:

• CPU executes computational programs.
• IOP performs I/O housekeeping and data movement.
• Memory is the common exchange area.

A communication processor is an IOP specialized for serial links and remote terminals.

Check Your Understanding

1. What failure can a handshake detect that a one-way strobe cannot?
2. Why are RD and WR described as bidirectional at a DMA controller?
3. After 37 transfers from starting address 0x1200, what are address and count if the initial count was 100?
4. Which priority method encodes priority in cable order?
5. What capability separates an IOP from an ordinary DMA controller?